This present invention relates to a comparison circuit for a semiconductor testing apparatus for testing a semiconductor device, and more particularly, to a comparison circuit which compares an output from a device under test with an expected signal at a timing of strobe signal with larger margin and flexibility in setting the strobe timing.
Semiconductor device tests by a semiconductor testing apparatus includes a GO/NO-GO (pass/fail) test of an output from a device under test (hereinafter referred to as DUT) by a timing of a strobe signal.
FIG. 4 shows an example of block diagram of a conventional comparison circuit used in a semiconductor testing apparatus to perform the GO/NO-GO test by the timing of the strobe signal.
In FIG. 4, level (analog) comparators (5, 6) compare the output signal of DUT 1 with reference voltage signals. The level comparator 5 compares the DUT's output signal with a high voltage reference signal (VOH) for detecting a high level of the output signal and generates an output signal SH when the output signal from the DUT reaches the reference voltage VOH. The level comparator 6 compares the DUT's output signal with a low voltage reference signal (VOL) for detecting a low level of the output signal and generates an output signal SL when the output signal from the DUT reaches the reference voltage VOL. The output signals SE and SL are given to a digital comparison circuit 4.
A timing generator 3 generates strobe signals (STBH, STBL) for executing logical comparison in the digital comparison circuit 4. The strobe signals STBH and STBL are given to the digital comparison circuit 4 to determine the timing of the comparison. In the timing generator 3, the strobe signals STBE and STBL are generated on the basis of timing data stored in a memory 31. A pattern generator 2 sends a control signal (TEST) to the memory 31 to read the timing data from the memory 31.
The pattern generator 2 also sends an expected value signal (EXP) which periodically varies its high/low logic state and a system clock (SCLK) to the digital comparison circuit 4. The system clock is used as a time reference of overall operation of the semiconductor testing apparatus.
The digital comparison circuit 4 compares the logic states of the output signals SH and SL from the level comparators 5 and 6 with the expected value signals at the timings of the strobe signals STBH and STBL and outputs comparison results (COR). In a semiconductor testing apparatus, it is usually desired that such comparison results be taken out in synchronism with the system clock SCLK because, for example, of convenience in signal processes at later stages of the testing apparatus. Further, since the timings of the strobe signals vary depending on the timing data from the memory 31, phases of the strobe signals STBH and STBL are usually different from those of the system clock. Thus, the comparison circuit includes a circuit arrangement for sampling (latching) the output signals SH and SL by the timings of the strobe signals and re-timing comparison results between the sampled output signals and the expected value signals to be synchronized with the system clock SCLK.
FIG. 5 shows the configuration of the conventional digital comparison circuit 4. As shown in FIG. 5, the output signal SH from the level comparator 5 is latched by a buffer 42 at the timing of the strobe signal STBE and stored in a flip-flop 43 at the timing of the strobe signal through a delay element 45. The output signal SL from the level comparator 6 is latched by a buffer 46 at the timing of the strobe signal STBL and stored in a flip-flop 47 at the timing of the strobe signal through a delay element 49. The data in the flip-flops 43 and 47 are respectively provided to interleave writing circuits 44 and 48 wherein the data is written therein in a time divisional manner. The data in the interleave writing circuits 44 and 48 and then read out by interleave reading circuits 33 and 34 and compared with the expected value signals by a logic comparator 41. The expected value signals are in synchronism with the system clock SCLK.
An example of interleave circuit is shown in FIG. 8. The example of FIG. 8 includes both an interleave writing circuit and an interleave reading circuit. The interleave writing circuits 44 and 48 correspond to the left side of FIG. 8 and the interleave reading circuits 33 and 34 correspond to the right side of FIG. 8. Each of the interleave writing circuits 44 and 48 includes an input flip-flop 60, a plurality of multiplexers 51.sub.1 -51.sub.4, a counter 52 and a plurality of flip-flops 54.sub.1 -54.sub.4. The strobe signal is provided to the counter 52 and the flip-flops 54.sub.1 -54.sub.4. Thus, every time the counter 52 receives the strobe signal, a control signal from the counter 52 sequentially selects one of the multiplexers 51.sub.1 -51.sub.4. As a result, the incoming data through the flip-flop 60 is sequentially divided in the flip-flops 54.sub.1 -54.sub.4 in synchronism with the strobe signal. In other words, the interleave writing circuit in FIG. 8 functions as a serial-parallel converter by the timing of the strobe signals.
Each of the interleave reading circuits 33 and 34 includes a counter 56, a multiplexer 58 and an output flip-flop 62. The counter 56 and the output flip-flop 62 are provided with the system clock. A control signal from the counter 56 is provided to the multiplexer 58. Thus, every time the counter 56 receives the system clock, the multiplexer sequentially selects the data from one of the flip-flops 54.sub.1 -54.sub.4 and the data is taken out through the output flip-flop 62 in a serial form in synchronism with the system clock. In other words, the interleave reading circuit in FIG. 8 functions as a parallel-serial converter by the timing of the system clock.
By the procedure described above, the output signals SH and SL from the level comparators 5 and 6 which are latched by the timing of the strobe signals are timing adjusted to synchronize with the system clock. Since the system clock SCLK and the strobe signals STBH and STBL are used to sequentially drive the interleave circuit, both of the strobe signals and the system clock must be constantly applied to the interleave circuit so as to keep the sequence of data in the circuit in order.
FIG. 6 shows the timing chart involving the strobe signal in the conventional comparison circuit. OUT1, OUT2, OUT3 . . . OUT7 shown in FIG. 6B which are output signals of DUT are applied to a digital comparison circuit 4. The expected value signal levels corresponding to the output signals are H, L, H . . . Z, respectively, in FIG. 6A. The strobe signal STBH for a high level and the strobe signal STBL for a low level are applied to the comparison circuit as shown in FIGS. 6C and 6D.
As described above, the interleave operation requires continuous application of the strobe signals STBH and STBL to the interleave circuit. For example, the strobe signal STBH for the high level must be output even for an expected value signal is in the low level as in the situations of OUT2 or OUT6. In such situations, the strobe signal STBE is unnecessary as far as the logical comparison is concerned since the expected value only requires the low level output. Similarly, the strobe signal STBL for the low level must be output even for an expected value signal is in the high level as in the situations of OUT1, OUT3 or OUT4. Although not shown in the timing chart, some test cycles do not need to compare the device output and the expected value at all, which is usually called a "don't care" situation. Even in such a situation, the strobe signal must be supplied to the interleave circuit to maintain the sequential order in the circuit. In FIG. 6A, a reference "Z" in the expected value means high impedance condition in the output of the device under test which requires both strobe signals STBH and STBL for its evaluation.
As noted above, the timings of the strobe signals are variable in the testing apparatus so that the phases of the strobe signals change within the test cycle. Generally, a strobe interval, i.e., a time difference between the adjacent strobe signals, has a limitation called a close limitation. That is, an available minimum strobe interval corresponds to the maximum logic operating rate of the timing generator and digital comparison circuit. Therefore, as increasing the operating rate of the testing apparatus, the available range of the strobe interval necessarily becomes shorter. Further, if the operating rate of the testing apparatus is set to a maximum, the strobe timing results to be limited to the minimum interval of the operating rate.
In the conventional comparison circuit for a semiconductor testing apparatus has a disadvantage in that the strobe signal must be supplied to the comparison circuit even it is unnecessary in the comparison purpose and the timing between the strobe signals tend to be limited to the close limitation.